Conventional multilevel metal processes typically form a plurality of levels of interconnects that are connected to one another with via structures. Typically, a first metal layer is formed over an underlying insulating layer and then patterned to form the first level interconnects from the first metal layer.
After forming the first level interconnects, an insulating layer is deposited over the first level interconnects and patterned to form via openings. The via openings are typically formed by coating a photoresist layer over the insulating layer and patterning it to form openings where the vias will be located. Next, the insulating layer is dry etched to expose a portion of the first level interconnects. During the via etch processing step, the etchants react with the oxide and the metal of the first level interconnects. Within a via opening, via veils typically form and are believed to include the metal of the first level interconnects, the material of the insulating layer, and the photoresist material. Via veils are extremely difficult to remove without severely damaging the exposed first level interconnects or eroding too much of the insulating or photoresist layers.
Via veils can be avoided by forming a stack of at least one conductive material. The stack is twice etched before depositing an insulating layer over the stack. One of the two etch steps defines portions of the stack where vias to an overlying interconnect level are subsequently formed, and the other step forms the general pattern of the interconnects underlying the via portions. The stack is two or more times as thick as a metal layer used to form interconnects.
An insulating layer is deposited over the etched structure after the two etching steps. The vertical distance between the underlying insulating layer and the top of the via portions is extremely large. In many instances, the height difference is typically 1.5-2.0 microns. Step coverage issues and planarizing are major concerns with the device at this process because of the large height difference. Regarding the surface area of the device, the vias make up only a small portion of the total device area.
After depositing the insulating layer over the first level interconnect, the portion of the insulating layer over the via portions of the first level interconnects is removed. Typically, a polishing or etch back process is used. However, these processes can remove too much of the insulating layer and via portions. The via portions occupy only a small portion of the device area making them a poor polish-stop or etch-stop layer. The parasitic capacitive coupling can be too high between the first level interconnect and a second level interconnect if too much of the via portions and insulating layer are removed. In severe cases, an electrical short could result between first and second level interconnects that are not to be electrically connected.
A need exists to form a reliable interconnect structures that are relatively easy to fabricate without having to develop new or marginal processing steps. The process should not form via veils.